AT-1212 FlexRIO模組

AT-1120 / AT-1212 WIDEBAND, HIGH RESOLUTION ARBITRARY WAVEFORMS

New Generation Waveforms for Complex Real-World Signals

High bandwidth and high resolution AWGs help you to generate with confidence complex signals like digital modulations and RF stimuli for functional and performance tests.

AT-1212, by combining 1.25 GS/s with 14 Bit Bit Vertical Resolution, gives you high performance analog and digital waveforms to meet demanding for test signals and applications where speed, resolution and quality is an issue.

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Functions:

• RF Signal Generation

• Digital Modulations

• Extended waveform memory by using FlexRio onboard DRAM

• Very Low Harmonic Distortion

• Arbitrary and DDS modes

• Real Time Data Streaming and Processing

• LabView FPGA Graphical Programming

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Specifications:

Model No.	AT1120			AT-1212
Specifications
Number of Analog Channels	1			2
DAC Resolution	14 Bit			14 Bit
Sampling Rate	2 GS/s			1.25 GS/s
DC-coupled analog output
Characteristics	DC Output
Output type	Single ended or differential
Impedance	50 Ω / 100 Ω			50 Ω / 100 Ω
Amplitude1 , 50 Ω Load (1KHz sine wave)
Full Scale Range, Single Ended Fulle Scale Range, Differential Resolution	1 Vp-p (1.1Vpp without calibration) 2 Vp-p (2.2 Vpp without calibration) 3 digits, < ± (0.07% of amplitude range), <1mV			2 Vp-p (2.2Vpp without calibration) 4 Vp-p (4.4 Vpp without calibration) 3 digits, < ± (0.07% of amplitude range), <1mV
Vocm (Output common mode voltage)
Range Resolution, 50 Ohm load	-0.9 V to 0.9V Open, -0.45V to 0.45V@50 Ω load <10mV			-1.6V to 1.6V Open, -0.8V to 0.8V@50 Ω load <5mV
Channel-to-channel Skew, typ @1.25GS/s				50 ps
Rise time (10% to 90%)	340 ps (Pulse at 0.5 Vp-p S.E.)			500 ps (Pulse at 1 Vp-p S.E.)
Fall time (10% to 90%)	340 ps (Pulse at 0.5 Vp-p S.E.)			550 ps (Pulse at 1 Vp-p S.E.)
Bandwidth (0.35/Trise)	1 GHz, typical (calculated)			700 MHz, typical (calculated)
Analog Bandwidth,	1 GHz (compensating for DAC sin(x)/x roll-off), typical [-2 dBm (sine wave at 0.5 Vpp)]			650 MHz (compensating for DAC sin(x)/x roll-off), typical [+4dBm (sine wave at 1 Vpp)]
Analog Bandwidth,	750 MHz (compensating for DAC sin(x)/x roll-off), typical 550 MHz (not compensating for DAC sin(x)/x roll-off), typica [+3 dBm (-1dBFs) (sine wave at 0.9 Vpp]			500 MHz (compensating for DAC sin(x)/x roll-off), typical 400 MHz (not compensating for DAC sin(x)/x roll-off), typical [+9dBm (-1dBFs) (sine wave at 1.8 Vpp)]
Overshoot	Less than 5% (at 0.5Vp-p)			Less than 5% (at 1Vp-p)
Random Jitter on clock pattern, typ	<5 ps			<5 ps
SFDR (including Harmonics)2 @ 2GS/s, typical Sine Wave (62.5001 MHz) Sine Wave (125.0002 MHz) Sine Wave (250.0004 MHz)	S.E. (DC to 800MHz)   -67 dBc, 0.5Vp-p -66 dBc, 0.5p-p -57 dBc, 0.5p-p	Diff. (DC to 800MHz) -71 dBc, 1Vp-p -66 dBc, 1Vp-p -58 dBc, 1Vp-p		S.E. (DC to 480MHz) -71 dBc,1Vp-p -57 dBc, 1Vp-p -44 dBc, 1Vp-p		Diff. (DC to 480MHz) -69 dBc, 2Vp-p -67 dBc, 2Vp-p -58dBc, 2Vp-p
Non Harmonic Distortion, typical	-79 dBc, 1Vp-p, DC to 800 MHz			-77 dBc, 1Vp-p, DC to 480 MHz
Phase noise Internal clock, typical	10 MHz	62.5 MHz (32 points waveform)	110 MHz	10 MHz	39.0625 MHz (32 points waveform)	110 MHz
1 KHz offset	-126 dBc/Hz	-110 dBc/Hz	-107 dBc/Hz	-128 dBc/Hz	-116 dBc/Hz	-107 dBc/Hz
10 KHz offset	-137 dBc/Hz	-123 dBc/Hz	-118 dBc/Hz	-136 dBc/Hz	-127 dBc/Hz	-118 dBc/Hz
100 KHz offset	-148 dBc/Hz	-137 dBc/Hz	-131 dBc/Hz	-148 dBc/Hz	-139 dBc/Hz	-130 dBc/Hz
1 MHz offset	-154 dBc/Hz	-153 dBc/Hz	-152 dBc/Hz	-153 dBc/Hz	-152 dBc/Hz	-151 dBc/Hz
AO 0+ / AO 0-	DC Output			AO 0+ / AO 0- / AO 1+ / AO 1- /DC Amplified Output
Output connector	SMA
Output impedance	50Ω S.E. / 100Ω Diff.
Io max @ 50 Ohm load	22 mA			44 mA
External Clock IN
Input connector	SMA
Input Voltage Range	-10 dBm to 8 dBm
Impedance	50 Ω, AC Coupled
Frequency	2 GHz (within ±0.1%)			1.25 GHz (within ±0.1%)
Damage Level	+14 dBm MAX ±25VDC MAX
External Trigger Input
Input connector	SMA
Max data rate	140 Mbps
Input impedance	100K Ω
Trigger Level VIH min VIL max	1.75V 0.75V
Damage level	VINmax < 6.5 V VINmin > -0.5V
Slope	Rising Edge or Falling
External Trigger Output
Output connector	SMA
Output level	3.3V open, 1.65V with 50 Ohm load
Output impedance	50 Ohm nomina

¹ Gain,offset,Vocm calibrated
² Waveforms were generated using DDS (Direct Digital Synthesis) with a waveform table size of 2048 samples and a phase accumulator of 32 bits. Long, non-repetitive, waveforms such as modulated or DDS (Direct Digital Synthesis)- based signals offer better spurious performance.

For periodic waveforms represented by a small number of unique samples, DAC nonlinearities limit dynamic specifications. SFDR performance may be worse at signal frequencies near to integer submultiples of the sampling frequency due to harmonic stacking on images (ex. Fs/N with N=8,16,32).